1. Field of the Invention
This invention relates to semiconductor device fabrication, and in particular a method of forming a GaAs semiconductor MESFET device using a self-aligned gate process and a lift-off technique.
2. Description of the Prior Art
There has been a variety of self-aligned gate processes that have been utilized in gallium arsenide (GaAs) integrated circuit fabrication. One of the more important techniques is the so-called T-gate process for ion implantation, described in "Self-Aligned Submicron Gate Digital Integrated Circuits", H. M. Levy and R. E. Lee, IEEE Elec. Div. Letters, EDL-4 pp. 102-104, 1983 and "Fabrication and Performance of Submicron Gallium Arsenide MESFET Digital Circuits by Self Aligned Ion-Implantation", R. A. Sadler, Ph.D. thesis, Cornell University, January, 1984.
The T-gate structure itself consists of two metal layers. The top metal layer is defined by a lift-off process and serves as a mask for both plasma etching and ion implantation. It is first used to reactive-ion etch the underlying refractory gate metal, with an intentional undercut on each side to form the T-gate structure. This structure then masks the device channel for a self-aligned n.sup.+ implant, so that the lateral gap between gate edge and n.sup.+ regions can be made quite shallow with high surface doping without increasing the gate capacitance. The high doping at the surface reduces the ohmic contact resistance, and the shallow n.sup.+ regions minimize short-channel effects.
The principal disadvantage of the existing T-gate process is two-fold. First, the number of process steps required to complete the fabrication can dramatically decrease yield. Second, the gate Schottky barrier height, which plays a critical role on device performance, can vary with surface condition. In a conventional T-gate process the channel is annealed before deposition of the gate material and cannot be cleaned by etching without considerably complicating the processing sequence. As a result, existing T-gate processes are impractical for high volume production processes of GaAs integrated circuits.
There are other self-aligned gate processes for GaAs, such as described in the paper, "Self-Aligned Pt-Buried Gate FET Process with Surface Planarization Techniques for GaAs LSI" by T. Terada et al, IEEE GaAs IC Symposium IEEE Press, New York (1983), but such techniques do not significantly decrease the fabrication complexity or yield a uniform Schottky barrier gate height across the wafer.
Another method is disclosed in U.S. Pat. No. 4,404,732, issued Sept. 20, 1983 to Andrade, which describes a fabrication process of a gallium arsenide MESFET device which provides for the in situ growth of self-aligned, raised source and drain regions. One feature is placing a high temperature resistant gate structure, such as tungsten, on the gallium arsenide substrate. Then by a process, including molecular beam epitaxy, growing epitaxial gallium arsenide on each respective side of the gate so as to form a raised source region and a raised drain region. The MESFET channel region, which is defined by the proximate edges of the source and the drain, is self-aligned with the edges of the gate by virtue of the in situ process for the formation of the source and drain.
Prior to the present invention, there has not been a process which provides a self-aligned GaAs device with a limited number of simple processing steps.